New Delhi, June 4(CXO Media): IIT Delhi and Cadence have launched a joint innovation lab aimed at strengthening semiconductor design education and research in India.
The Indian Institute of Technology Delhi IIT Delhi and Cadence Design Systems Cadence Design Systems have set up a semiconductor-focused innovation lab centered on electronic design automation (EDA) tools and AI-enabled chip design workflows. The initiative is designed to improve hands-on training in chip design and bridge the gap between academic learning and industry requirements.
The lab will provide access to more than 200 EDA tools covering chip design verification, digital implementation, analog design, and system-level analysis. These tools are used in real-world semiconductor development and pre-silicon design workflows.
IIT Delhi has introduced Cadence-developed modules into its curriculum, shifting emphasis toward project-based learning using industry-style chip design problems. The approach is intended to make students more familiar with tools and processes used in semiconductor companies.
The programme also includes an early master’s research track for selected undergraduate students from IITs and NITs. In addition, a startup support pathway will help early-stage semiconductor ventures access tools and mentorship for prototype development and tape-out readiness.
The initiative aligns with India’s semiconductor strategy, including the India Semiconductor Mission and the Design Linked Incentive (DLI) scheme, which focus on building domestic chip design capability and strengthening the skilled talent pipeline.
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