New Delhi: Prime Minister Narendra Modi, accompanied by IT Minister Ashwini Vaishnaw and MoS Jitin Prasada, visited exhibition stalls at the Semicon India 2025 in Yashobhoomi,  where Indian startups unveiled their latest innovations in semiconductor design.
The focus was on Design Linked Incentive (DLI)-backed projects and breakthroughs in RISC-V platforms, reflecting India’s growing self-reliance in chip design and intellectual property creation.
The government’s DLI Scheme has emerged as a key driver of India’s fabless ecosystem, supporting 23 chip design projects while giving 72 startups access to advanced Electronic Design Automation (EDA) tools.
Many of these companies presented their solutions at the event, spanning surveillance, networking, motor control and energy metering, signalling a robust pipeline of indigenous designs ready for scale-up.
A highlight was InCore Semiconductors’ RISC-V-based System-on-Chip Generator Platform, which reduces frontend chip design time from months to minutes, enabling faster innovation cycles.
A test chip taped out on TSMC’s 40nm process showcased six heterogeneous RISC-V cores, advanced NoC bridging and a complete RTOS software stack. InCore also announced three processor families — Azurite for ultra-low power, Calcite for balanced performance and Dolomite for high-performance vector processing.
Other major unveilings included Aheesa Digital Innovations’ Vihaan SoC, built on C-DAC’s VEGA processor for broadband and networking, and CCTV-focused solutions from 3rdiTech, Netrasemi, BigEndian and Mindgrove, which collectively raised over Rs 300 crore in VC funding. MosChip demonstrated progress on its Vidyut Smart Energy Meter chip, while Vervesemi advanced indigenous ICs for EV motor control and ISRO space applications.
MBit Wireless also showcased its indigenously developed 4G-LTE modem chipset, already certified and under field trials with telecom operators.
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